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MC74VHC14 Hex Schmitt Inverter
The MC74VHC14 is an advanced high speed CMOS Schmitt inverter fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. Pin configuration and function are the same as the MC74VHC04 but the inputs have hysteresis and, with its Schmitt trigger function, the VHC14 can be used as a line receiver which will receive slow input signals. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems.
Features
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14 SOIC-14 D SUFFIX CASE 751A 1 VHC14G AWLYWW
* * * * * * * * * *
High Speed: tPD = 5.5 ns (Typ) at VCC = 5.0 V Low Power Dissipation: ICC = 2.0 mA (Max) at TA = 25C High Noise Immunity: VNIH = VNIL = 28% VCC Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2.0 V to 5.5 V Operating Range Low Noise: VOLP = 0.8 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: Human Body Model > 2000 V; Machine Model > 200 V Chip Complexity: 60 FETs or 15 Equivalent Gates
A = Assembly Location WL, L = Wafer Lot Y = Year WW, W = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location) TSSOP DT SUFFIX CASE 948G 1 14 VHC 14 ALYW G G
* * Pb-Free Packages are Available
VCC 14 A6 13 Y6 12 A5 11
FUNCTION TABLE
Y5 10 A4 9 Y4 8 Inputs A L H Outputs Y H L
1 A1
2 Y1
3 A2
4 Y2
5 A3
6 Y3
7 GND
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet.
Figure 1. 14-Lead Pinout (Top View)
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
1
February, 2006 - Rev. 9
Publication Order Number: MC74VHC14/D
MC74VHC14
A1 1 2 Y1 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open.
A2
3
4
Y2
A3
5
6
Y3 Y=A
A4
9
8
Y4
A5
11
10
Y5
A6
13
12
Y6
Figure 2. Logic Diagram MAXIMUM RATINGS
Symbol VCC VIN VOUT IIK IOK IOUT ICC PD TSTG VESD Positive DC Supply Voltage Digital Input Voltage DC Output Voltage Input Diode Current Output Diode Current DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air Storage Temperature Range ESD Withstand Voltage Human Body Model (Note 1) Machine Model (Note 2) Charged Device Model (Note 3) Above VCC and Below GND at 125C (Note 4) SOIC TSSOP SOIC TSSOP Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC +0.5 -20 $20 $25 $75 200 180 -65 to +150 >2000 >200 N/A $300 143 164 Unit V V V mA mA mA mA mW C V
ILATCHUP qJA
Latchup Performance
mA C/W
Thermal Resistance, Junction-to-Ambient
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Tested to EIA/JESD22-A114-A. 2. Tested to EIA/JESD22-A115-A. 3. Tested to JESD22-C101-A. 4. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN VOUT TA tr, tf DC Supply Voltage DC Input Voltage DC Output Voltage Operating Temperature Range, All Package Types Input Rise or Fall Time VCC = 3.3 V + 0.3 V VCC = 5.0 V + 0.5 V Characteristics Min 2.0 0 0 -55 - - Max 5.5 5.5 VCC 125 No limit No limit Unit V V V C ns/V
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5. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 6 (per buffer). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
III I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I II I I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I III I III I I IIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIII I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I IIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I IIIII I IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I I IIIIIIIIIIIIIIIIIIIII IIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I IIIII I IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIII III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I IIIII II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIII I I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I I I IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I I I I I IIIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII III I I IIIII II I I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns) DC ELECTRICAL CHARACTERISTICS
Symbol Symbol tPLH, tPHL VOH CPD VOL VT+ VT- ICC Cin VH Iin Power Dissipation Capacitance (Note 5) Maximum Input Capacitance Maximum Propagation Delay, A or B to Y Maximum Quiescent Supply Current Maximum Input Leakage Current Maximum Low-Level Output Voltage Minimum High-Level Output Voltage Hysteresis Voltage (Figure 5) Negative Threshold Voltage (Figure 5) Positive Threshold Voltage (Figure 5) Parameter Parameter VCC = 5.0 0.5 V VCC = 3.3 0.3 V Vin = VCC or GND Vin = 5.5 V or GND Vin = VIH or VIL Vin = VIH or VIL IOL = 50 mA Vin = VIH or VIL Vin = VIH or VIL IOH = - 50 mA Test Conditions Test Conditions IOH = - 4 mA IOH = - 8 mA CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF IOL = 4 mA IOL = 8 mA
NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V)
Symbol
VOLP
VOLV
VIHD
VILD
Maximum Low Level Dynamic Input Voltage
Minimum High Level Dynamic Input Voltage
Quiet Output Minimum Dynamic VOL
Quiet Output Maximum Dynamic VOL
Characteristic
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MC74VHC14
3 0 to 5.5 VCC V 5.5 3.0 4.5 2.0 3.0 4.5 3.0 4.5 2.0 3.0 4.5 3.0 4.5 5.5 3.0 4.5 6.0 3.0 4.5 5.5 Min 0.9 1.35 1.65 2.58 3.94 0.30 0.40 0.50 Min TA = 25C 1.9 2.9 4.4 Typical @ 25C, VCC = 5.0 V 8.3 10.8 Typ 5.5 7.0 4 TA = 25C Typ 0.0 0.0 0.0 2.0 3.0 4.5 8.6 10.6 12.8 16.3 Max 10 21 0.1 0.36 0.36 1.20 1.40 1.60 2.20 3.15 3.85 Max 2.0 0.1 0.1 0.1 -0.4 -55C TA 125C Typ 0.4 -55C TA 125C Min 1.0 1.0 1.0 1.0 2.48 3.80 0.30 0.40 0.50 0.90 1.35 1.65 Min TA = 25C 1.9 2.9 4.4 -0.8 Max 1.5 3.5 0.8 10.0 12.0 15.0 18.5 Max 1.0 20.0 0.44 0.44 1.20 1.40 1.60 2.20 3.15 3.85 Max 10 0.1 0.1 0.1 Unit Unit Unit mA mA pF pF ns V V V V V V V V V
MC74VHC14
TEST POINT VCC A 50% GND tPLH Y 50% VCC *Includes all probe and jig capacitance tPHL DEVICE UNDER TEST OUTPUT CL*
Figure 3. Switching Waveforms
Figure 4. Test Circuit
V T , TYPICAL INPUT THRESHOLD VOLTAGE (VOLTS)
4
3 (VT+) VHtyp
2 (VT-)
1
2
3
4
5
6
VCC, POWER SUPPLY VOLTAGE (VOLTS) VHtyp = (VT+ typ) - (VT- typ)
Figure 5. Typical Input Threshold, VT+, VT- versus Power Supply Voltage
VH Vin
VCC VT+ VT- GND VOH Vin
VH
VCC VT+ VT- GND VOH
Vout VOL (a) A Schmitt-Trigger Squares Up Inputs With Slow Rise and Fall Times
Vout VOL (b) A Schmitt-Trigger Offers Maximum Noise Immunity
Figure 6. Typical Schmitt-Trigger Applications
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MC74VHC14
ORDERING INFORMATION
Device MC74VHC14D MC74VHC14DG MC74VHC14DR2 MC74VHC14DR2G MC74VHC14DT MC74VHC14DTG MC74VHC14DTR2 MC74VHC14DTR2G Package SOIC-14 SOIC-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) TSSOP-14* TSSOP-14* TSSOP-14* TSSOP-14* Shipping 55 Units / Rail 55 Units / Rail 2500 / Tape & Reel 2500 / Tape & Reel 96 Units / Rail 96 Units / Rail 2500 / Tape & Reel 2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
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MC74VHC14
PACKAGE DIMENSIONS
SOIC-14 D SUFFIX CASE 751A-03 ISSUE G
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
-A-
14 8
-B-
P 7 PL 0.25 (0.010)
M
B
M
1
7
G C
R X 45 _
F
-T-
SEATING PLANE
D 14 PL 0.25 (0.010)
K
M
M
S
J
TB
A
S
DIM A B C D F G J K M P R
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MC74VHC14
PACKAGE DIMENSIONS
TSSOP-14 DT SUFFIX CASE 948G-01 ISSUE A
14X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
N
2X
L/2
14
8
0.25 (0.010) M
L
PIN 1 IDENT. 1 7
B -U-
N F DETAIL E K K1 J J1
0.15 (0.006) T U
S
SECTION N-N -W-
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
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PUBLICATION ORDERING INFORMATION
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CCC EEE CCC EEE CCC
A -V-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
DIM A B C D F G H J J1 K K1 L M
MC74VHC14/D

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